This invention relates to the field of data processing systems. More particularly, this invention relates to the scheduling of program instructions within data processing systems.
It is known to provide data processing systems including a plurality of execution circuits/units which execute a common program as a respective plurality of threads of program execution. Such data processing systems are sometimes termed single instruction multiple thread (SIMT) processors. The aim within such processors is that each of the execution units should execute the same block of code in lockstep with respect to the other execution units. This permits a saving in the amount of instruction decode circuitry that need be provided together with increasing the likelihood of achieving efficiency gains in memory accesses due to the memory accesses being correlated in a manner which permits them to be performed more efficiently. While each of the threads executes a common program, there may be points of divergence (branches) and convergence within the respective execution paths followed in the different threads executed upon the different execution units. This will result in some of the threads dropping out of lockstep operation and then resuming lockstep operation at a later time when they can be brought back to the same execution point.